In the test of a semiconductor memory device, one of voltages Vcc (power supply voltage), 1/2 Vcc and 0 (ground) is applied to an opposite electrode of a memory cell, so that the short-circuit of the memory cell, the current leakage to a semiconductor substrate, etc. are examined.
One of test voltage applying circuits comprises an intermediate voltage generating circuit for generating the voltage of 1/2 Vcc, a first NMOS transistor positioned between the intermediate voltage generating circuit and a cell opposite electrode, a PMOS transistor positioned between a power supply of the voltage Vcc and the cell opposite electrode, and a second NMOS transistor positioned between the cell opposite electrode and ground.
In operation of the test, the 1/2 Vcc voltage is applied to the cell opposite electrode at a state of the turning-off of the first and second NMOS transistor and the PMOS transistor, and the Vcc and 0 (ground) voltages are applied to the cell opposite electrode separately at states of the turning-off of the first and second NMOS transistors and the turning-on of the PMOS transistor, and of the turning-off of the first NMOS transistor and the PMOS transistor and the turning-on of the second NMOS transistor.
In this test, the respective voltages are applied to pads provided on a chip to be connected to the cell opposite electrode. For this structure, the test can be carried out only before assembling the chip as a semiconductor device.
A test voltage applying circuit, in which the test can be carried out even after the assembly of a semiconductor memory device, comprises a high voltage decision circuit connected to an input pin which is connected to an internal circuit of the memory device, a NOR circuit having first and second inputs connected to first and second outputs of the high voltage decision circuit, a first PMOS transistor connected at a gate to the first output of the high voltage decision circuit, and at a source to a power supply of Vcc, a second PMOs transistor connected at a gate to an output of the NOR circuit, and at a source to the first PMOS transistor, an intermediate voltage generating circuit for generating a 1/2 Vcc voltage, a first NMOS transistor connected at a gate to the output of the NOR circuit, at a source-drain path to a drain of the second PMOS transistor and ground, and a second NMOS transistor connected at a gate to the first output of the high voltage decision circuit, and at a source-drain path to the intermediate voltage generating circuit, a cell opposite electrode, and a nodal point between the second PMOs transistor and the first NMOS transistor.
In operation of the test, an increasing voltage is applied through the input pin to the high voltage decision circuit. In this situation, when the increasing voltage ranges between the power supply voltage Vcc and a first predetermined voltage V.sub.1 (&gt;Vcc), high logic signals are generated at the first and second outputs of the high voltage decision circuit, so that the second NMOs transistor is turned on to apply the 1/2 Vcc voltage from the intermediate voltage generating circuit to the cell opposite electrode, while the first PMOs and NMOS transistors are turned off. When the increasing voltage becomes a level between the first predetermined voltage V.sub.1 and a second predetermined voltage V.sub.2 (&gt;V.sub.1), the first and second outputs of the high voltage decision circuit become low and high, respectively, so that the first and second PMOS transistors are turned on to apply the power supply voltage Vcc to the cell opposite electrode, while the first and second NMOS transistors are turned off. Further, when the increasing voltage becomes the second predetermined voltage V.sub.2, both the first and second outputs of the high voltage decision circuit become low, so that the first NMOS transistor is turned on to apply 0 (ground) voltage to the cell opposite electrode, while the second PMOS and NMOS transistors are turned off (although the first PMOS is turned on). Thus, the test can be carried out to apply the voltages Vcc, 1/2 Vcc and 0 to the cell opposite electrode, respectively, even after the assembly of a semiconductor memory device.
This test circuit, however, has a disadvantage in that the semiconductor memory device can not operate, because a voltage greater than a power supply voltage is applied to one of input pins.